Schönhage's SMM 8-bit Set Operation on Verilog

http://tinyurl.com/q9x9k4c

module smm(clk, dst, src, idx, val);
	input clk;
	input [3:0] dst;
	input [3:0] src;
	output [7:0] idx;
	output [7:0] val;

	reg [7:0] ram [0:255];

	wire [7:0] map [0:15];

	assign map[0] = 8'b0;

	genvar i;

	generate
		for (i = 1; i < 16; i = i + 1) begin: anl
			if (i % 2)
				assign map[i] = map[i / 2] + 1;
			else
				assign map[i] = ram[map[i / 2]];
		end
	endgenerate

	assign idx = map[dst];
	assign val = map[src];

	always @(posedge clk)
		ram[idx] <= val;
endmodule

`ifdef SIM
module sim;
	reg clk = 1'b0;
	reg [3:0] dst = 4'b1;
	reg [3:0] src = 4'b1;

	wire [7:0] idx, val;

	smm blk(clk, dst, src, idx, val);

	always begin
		if ($time >= 20)
			$finish;

		#1 $display(val);
		#1 clk <= ~clk;
		#1 clk <= ~clk;
		#1 src <= 4'b101;
	end
endmodule
`endif